The present invention relates in general to integrated circuits and in particular to current source circuits with improved power supply rejection.
Current sources are typically used in integrated circuits to set up the DC operating point (or biasing condition) of the circuit. The output of a current source is replicated (or multiplied by a factor) by current mirror circuits throughout a given circuit. As most of the operational parameters of a circuit depend on the DC operating point of that circuit, maintaining a constant bias condition is critical to the operation of the circuit. For example, it is often desirable to maintain a constant bias current even if the circuit power supply voltage varies. The ability of a circuit to resist changes in its operational parameters due to power supply voltage variations is commonly referred to as power supply rejection.
FIG. 1A shows an example of a mirroring current source circuit in bipolar technology. The current I.sub.1 is set by current source 100 which is typically a resistive element that is connected between a power supply independent voltage and a diode-connected transistor Q1. This current is mirrored by transistors Q1 and Q2 to generate I.sub.2, and mirrored again by transistors Q3 and Q4 to generate the output current I.sub.out. Variations in the power supply voltage of a conventional current mirror circuit such as the one depicted in FIG. 1A causes the output current I.sub.out to change. This is due to the fact that the collector current of a bipolar transistor increases slowly with increasing collector-emitter voltage. The mirrored current can be mathematically approximated using the following equations: ##EQU1## where V.sub.CE is the collector-emitter voltage of the indicated transistor and V.sub.AN and V.sub.AP are the Early voltages of the NPN and PNP transistors, respectively. Given a typical V.sub.CE value of 3 volts and an Early voltage of 30 V, I.sub.out would be more than 20% higher than I.sub.1. Thus, an error current results from what is referred to as the Early effect.
The collector-emitter voltage V.sub.CE is the power supply dependent term in the above equation. The impact of the V.sub.CE term can be minimized by maximizing the output impedance R.sub.out of the transistors in the circuit. That is, the power supply rejection of a typical current mirror is proportional to the output impedance, R.sub.out, of the transistors in the circuit. Higher output impedance results in higher power supply rejection. For the circuit shown in FIG. 1A, the output impedance of transistors Q2 and Q4 determine the level of power supply rejection. The output impedance of a transistor depends upon the fabrication process and the transistor geometry. With increasing emphasis on higher speed circuit fabrication processes, transistor sizes will continue to shrink. The smaller base widths of bipolar transistors and shorter gate lengths of field-effect transistors result in lower output impedances for these devices. Lower R.sub.out increases the circuit vulnerability to power supply variations.
Various techniques have been employed to increase the power supply rejection of a current mirror circuit. One approach is to increase device geometries (base widths or gate lengths). Increasing device geometries can be an option with MOSFETs or JFETs (longer channels) or with lateral bipolar transistors, because it can be readily implemented at the layout phase of the circuit (i.e., it does not require adjustments to the process). Longer base widths in vertical bipolar transistors, however, requires a longer and probably richer base diffusion. This requires a process change and may not even be feasible due to speed requirements for other transistors in the circuit. Also, many circuits are developed on general-purpose arrays of transistors. In such cases, the circuit designer does not have the freedom to adjust device geometries.
Another approach uses resistive degeneration to increase the effective output impedance. FIG. 1B shows the current mirror circuit of FIG. 1A with emitter degeneration resistors R.sub.e. The value for the output impedance R.sub.out of the current source in FIG. 1B is given by: ##EQU2## .beta.=common-emitter current gain of the transistors
R.sub.e =emitter degeneration resistance PA1 r.sub..pi. =(.beta.kT) / (qI.sub.B) PA1 r.sub.b =intrinsic base resistance PA1 R.sub.S =source impedance
If R.sub.e can be made large enough to dominate the denominator of the above equation, the output impedance of the current source can be approximately equal to .beta.R.sub.O, almost always an acceptably large value. Thus, emitter degeneration works well if the emitter resistor R.sub.e can be made large enough. With any significant output current from the current source, however, the voltage dropped across the emitter resistor can become too large to permit the use of this technique in a low voltage circuit. Thus, resistive degeneration is not a satisfactory solution for low voltage (e.g., around 3 volts) applications.
Another circuit technique to increase output impedance employs cascode devices. A well-known example of this circuit is the Wilson mirror circuit shown in FIG. 1C. A cascode device can provide very high output impedance, but it has the same limitation as the emitter degeneration resistor. That is, the voltage required for the operation of this circuit is increased by one V.sub.BE (base-emitter turn-on voltage of the cascode transistors) for each mirror. In the example of FIG. 1C, the voltage requirement of the circuit increases by 2 V.sub.BE. This is often more than the voltage that is available in the circuit.
A preferred technique for increasing the power supply voltage rejection of a cascaded current mirror while maintaining the low voltage operation is disclosed in the commonly-assigned U.S. patent application Ser. No. 08/398,235. There, the error current caused by the Early effect is detected, replicated, and then subtracted from the output current. FIG. 2 is a simplified circuit diagram of the low voltage current mirror circuit with improved power supply rejection. As fully described in the referenced U.S. patent application, block 204 generates the error current I.sub.err, which is mirrored by block 208 and subtracted from the output current I.sub.out. The error current subtraction cancels the impact of supply voltage variations. The circuit therefore exhibits improved power supply rejection.
One drawback of the error subtraction technique is that there is a subtraction transistor Q210 required for each output. That is, in those applications where the same reference current (I1 in FIG. 2) is to be used for generating multiple output currents, the subtraction transistor 210 must be repeated for each output. FIG. 3 shows the error subtraction technique applied to a cascaded current mirror with multiple outputs. It is shown that error subtraction transistors Q210, Q311, Q312, and Q313 must connect to the output nodes at the collector terminals of transistors Q212, Q314, Q315, and Q316, respectively. The number of additional transistors required to provide the correction increases linearly with the number of outputs. For a large number of outputs, this can quickly increase the size of the circuit.
It is therefore desirable to increase the power supply rejection of low voltage multiple output cascaded current mirror circuits without unduly increasing the circuit size.